搜索资源列表
DPRAM
- 网络控制器和链路控制器的CPU即是通过读写双端口RAM芯片完成网络层与数据链路层的原语交互。mailbox中写入的是原语的类型,而双端口RAM的其它存储空间则存放各种服务原语的参数。-network controller and the CPU controller link is through reading and writing dual-port RAM chip to complete the network layer and data link layer of the orig
一些VHDL源代码
- 内有波形发生器,加法器,经典双进程状态机,伪随机熟产生器,相应加法器的测试向量,16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
code-demo
- HM6264Driver_DS HM6264 RAM的读写驱动程序 S480_Manual_C S480的手动播放范例 (for SACMV26e.lib) SetIOBit SPCE061A 利用C语言进行软件端口位操作范例 ShowsinTable 简易正弦波发生器方案,同时提供全正数的正弦表 SleepTimerWakeup 定时中断唤醒CPU的范例 UARTDemo 使用UART中断方式进行通讯的范例 UARTDouble UART双机通讯范例,采用中断方
firm_usb
- DSP通过双口RAM和ISP1581实现下位机的USB固件程序,调试通过,上位机驱动和读写例程,如果下载多的话再传-DSP through dual-port RAM and ISP 1581 to achieve lower computer's USB firmware and Debugging, PC drivers and routines to read and write, if you download are so tame
allidt_20020616.tar
- idt的双口ram的读写接口程序,verilog 代码,并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
AT89S52
- Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz •
dpram_fpga
- 这是我用vhdl语言,在fpga内部做了一个双口ram的程序。我的邮箱:wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
my_ramlib_06
- 包括各种类型存储器的VHDL描述,如FIFO,双口RAM等 -including various types of memory VHDL descr iption, such as FIFO, Dual Port RAM, etc.
ram
- 利用verilog实现的双口RAM。文件包含工程文件,仿真文件,使用方便。-Using verilog implementation of dual-port RAM. File contains the project files, simulation files, easy to use.
dppramm
- 基于fpga的双口ram的设计与实现,好东西,希望大家喜欢-The dual-port ram fpga based design and implementation of good things, hope you like
RAM
- 基于verilog的双口和单口RAM的实现-Verilog dual port and single port RAM-based implementation
dual ram
- 此文件是FPGA工程文件,包含了dualram的设计代码和testbench代码,使用了verilog hdl编写,仿真结果符合设计要求。
DUAL-PORT-RAM
- vhdl使用双口RAM,工程编译通过。编译工具QUARTUS 9.0。-vhdl using the dual-port RAM, compiled by engineering.
ram
- 此文档为fpga控制双口RAM的开发文档,讲解很细,易于上手.双口RAM是在1个SRAM存储器上具有两套完全独立的数据线、地址线和读写控制线,并允许两个独立的系统同时对其进行随机性访问的存储器,即共享式多端口存储器。-This document is controlled dual-port RAM fpga development documents, explain very small, easy to use. Dual-port RAM is an SRAM memory has tw
ram
- 练习调用双口ram,fpga自产生65536个递增数,6.25Hz输出,在20ms内读出。-Exercises called dual port ram, fpga increasing number of self-produced 65536, 6.25Hz output within 20ms readout.
RAM
- Nios ii双口ram,用于MCU通过nios ii进行双口ram通信,verilog格式.-Nios II dual port RAM, for MCU dual port RAM communication, through the Nios II Verilog format.
DULE-RAM
- 基于VERILOG的双口ram例子,比较简单,不是很复杂,入门了解就可以了。-Based on dual port ram VERILOG example, the relatively simple, not very complicated, entry understand it.
dual-port-RAM
- 利用MegaWizard设计一个双端口RAM-Use MegaWizard design of a dual-port RAM
单片机(双核系统)
- 用了51单片机的ID工作方式,使没有HOLD功能的51单片机能够直接通过片外RAM进行数据通信。不但硬件和软件的实现都比较简单,数据传输速度快,而且不涉及高成本特殊器件,实现“双核系统”。(With 51 MCU ID works, make no HOLD function of 51 single-chip microcomputer can directly through the external RAM data communication. Not only the realizat
基于Actel-FPGA-的双端口RAM-设计
- 基于Actel-FPGA-的双端口RAM-设计(Base Actel-FPGA-Dual Port Ram design)